增强型串行外设接口（SPI0）（外文翻译及原文）-毕业作品网站

增强型串行外设接口（SPI0）提供了访问一个灵活的，全双工同步串行总线。SPI0可以工作在3线或4线模式作为主站或从站设备，并支持多个主机和从一个SPI总线上。从选择（NSS）信号可以被配置为输入在从模式选择SPI0或禁用主模式运行在多环境中，避免SPI总线上，当多个主设备试图同时进行数据传输的争夺。NSS也可以配置为片选在主模式下的输出，或禁用3线操作。额外的通用I / O端口引脚可以用来选择多个从器件在主模式。

主出从入（MOSI）信号是从一个主设备和从站设备的输入输出。它用于从主器件的从站的串行数据传输。这是一个信号输出时SPI0作为主输入时SPI0作为一个从属。数据传输最显着位第一。当配置为主机，MOSI由移位寄存器的MSB驱动两个3和4线模式。

主入从出（MISO）信号是从器件的输出和输入到主站设备。它是用来从从站到主站的串行数据传输。这是一个信号输入时SPI0作为一个主设备和一个输出时SPI0作为一个从属。数据传输最显着位第一。MISO引脚被放置在一个高阻抗状态时，SPI模块被禁止，当SPI在4线模式作为一个从属，是没有选择的。当作为一个从属在3线模式，MISO总是由移位寄存器的MSB驱动。

串行时钟（SCK）信号是从主设备和从站设备的输入输出。它是用来作为MOSI和MISO线主机和从机之间的数据同步传输。当SPI0作为主机工作时产生该信号。当从属是一个SPI从机的SCK信号被忽略在4线从模式选择（NSS =1）。

1. NSSMD[1:0]= 00：3线主方式或3线从方式：SPI0工作在3线模式，NSS被禁止。作为从设备操作时，SPI0总是被选择在3线模式。由于没有选择信号，SPI0必须是总线上唯一的从3线模式。这用于点到一个主机和一个从站之间的点对点通信。

2. NSSMD[1:0]= 01：4线从多主模式：SPI0工作在4线模式，NSS作为输入。作为一个从属，当操作NSS选择SPI0装置，。何时作为主，1到0过渡NSS信号禁用主站功能，SPI0，使多个主器件可用于同一SPI总线上。

SPI主设备启动SPI总线上的所有数据传输。SPI0被放置在主模式下，通过设置主允许标志（MSTEN，SPI0CN.6）。SPI0数据寄存器（SPI0DAT），当数据写入一个字节在主模式下，写入到发送缓冲区。如果SPI移位寄存器为空，发送缓冲区的字节移动到移位寄存器，数据传输开始。SPI0主立即移出数据在MOSI线上串行同时提供串行时钟（SCK）。 SPIF（SPI0CN.7）标志被设置为逻辑1，在传输结束。如果中断使能，则产生一个中断请求时，SPIF标志被设置。虽然SPI0主MOSI线数据传输到一个从站，被寻址的SPI从设备同时将其移位寄存器中的内容，SPI主控制器上的MISO线在全双工操作。因此，SPIF标志作为既是完成发送和接收数据准备好标志。该从站接收数据字节传输到主站的移位寄存器MSB优先。

当一个字节完全移入移位寄存器，它被转移到接收缓冲器，它可以读取处理器阅读SPI0DAT。当配置为主机，SPI0可以工作在三种不同的模式：多主方式，3线单主模式和4线单主方式。默认情况下，多主模式是积极的，当NSSMD1（SPI0CN.3）= 0和NSSMD0（SPI0CN.2）= 1。在这种模式下，NSS是输入到该设备，并用来禁用主SPI0当另一个主站正在访问总线。当NSS被拉低这种模式，将MSTEN（SPI0CN.6）和SPIEN（SPI0CN.0），被设置为0以禁用SPI主设备，一个模式故障产生（MODF，SPI0CN.5 = 1）的。模式故障会产生一个中断，如果启用。SPI0必须手动重新启用软件在这种情况下。在多主机系统中，设备将通常默认为被从设备，而他们不是作为系统主设备。在多模式下，从器件都可以被单独处理（如需要）使用通用I / O引脚。

3线单主模式被激活时，NSSMD1（SPI0CN.3）= 0和NSSMD0（SPI0CN.2）= 0。在这种模式，NSS未被使用，而不是映射到外部端口引脚通过横梁。任何从属设备必须在此模式下解决，应选择使用通用I / O引脚。

4线单主模式被激活时，NSSMD1（SPI 0CN.3）= 1。在这种模式下，NSS被配置为输出引脚，可以用来作为一个从属选择一个SPI器件的信号。在这种模式下的输出值NSS控制（软件）由NSSMD0（SPI0CN.2）。另外的从器件可以解决使用通用I / O引脚。

当SPI0启用，而不是作为主配置，它将作为一个SPI从属。作为一个从属，字节通过MOSI引脚移入，MISO引脚由主器件控制SCK信号。 SPI0逻辑中的位计数器计数SCK边缘。当8位数据通过移位寄存器转移，SPIF标志被设置为逻辑1，字节被复制到接收缓冲区。数据被读出阅读SPI0DAT接收缓冲区。从设备不能启动数据传送。要传输的数据的主设备已预先加载到移位寄存器写入SPI0DAT。写入SPI0DAT是双缓冲，并放在发送缓冲区中的第一。如果移位寄存器是空的，发送的内容缓冲区将立即被转移到移位寄存器。当移位寄存器已经包含数据，SPI将装入移位寄存器发送缓冲区的内容后，最后SCK（或当前）SPI传输。

当配置为从属，SPI0可以配置为4线或3线操作。默认情况下，4线从模式，是积极的，当NSSMD1（SPI0CN.3）= 0和NSSMD0（SPI0CN.2）= 1。在4线模式，NSS信号发送到一个端口引脚配置为数字输入。 SPI0时启用NSS为逻辑0，禁用NSS为逻辑1时。在NSS的下降沿，位计数器被重置。请注意，NSS信号必须被驱动前低至少2个系统时钟SCK每个字节传输的第一个活动的边缘。

3线从模式时是活跃NSSMD1（SPI0CN.3）= 0和NSSMD0（SPI0CN.2）= 0。NSS是不是在这种模式下，并没有映射到外部端口引脚横梁。由于没有办法唯一解决设备在3线从模式，SPI0必须是唯一的从器件上存在总线。重要的是要注意，在3线从模式，也没有外部手段对位计数器复位确定一个完整的字节时，已收到。位计数器只能通过禁用和重新启用SPI0 SPIEN位复位。

2. 写冲突标志WCOL（SPI0CN.6）被设置为逻辑1，如果尝试写SPI0DAT当发送缓冲区没有被掏空的SPI移位寄存器。当这种情况发生时，写SPI0DAT将被忽略，并且发送缓冲区不会发生写入。该标志适用于所有SPI模式。

3. 模式故障标志MODF（SPI0CN.5）被设置为逻辑1时SPI0作为主配置，多主模式和NSS引脚被拉低。当一个模式故障发生时，SPI0CN MSTEN和SPIEN位被设置为逻辑0禁用SPI0并允许另一个主的移动设备访问总线。

四个串行时钟相位和极性组合可以选择使用时钟控制位SPI0配置寄存器（SPI0CFG），CKPHA位（SPI0CFG.5）选择两种时钟相位（所用的边沿锁存的数据）。CKPOL位（SPI0CFG.4）之间进行选择的高有效或低有效时钟。主设备和从设备都必须配置主组分，使用相同的时钟相位和极性。SPI0应禁用（通过清除SPIEN位，SPI0CN.0）时改变时钟相位和极性。需要注意的是CKPHA必须被设置为'0'，在两个SPI主机和从机之间进行通信时，两个以下设备的C8051f04x，C8051F06X， C8051F12x/13x，C8051F31x，C8051F32X，C8051F33x。

SPI0时钟速率寄存器（SPI0CKR）在SFR控制主模式串行时钟频率。在从模式下操作时，该寄存器被忽略。当SPI配置作为主，最大数据传输速率（比特/秒）的一半的系统时钟频率12.5兆赫，较慢。当SPI配置作为一个从属，最高数据传输速率（比特/秒）全双工操作的系统时钟频率的1/10，但前提是主问题SCK，NSS（在4线从模式）和串行输入数据与从机系统时钟同步。如果主问题SCK，NSS和异步串行输入数据，最高数据传输速率（比特/秒）必须是系统时钟频率的1/10以下。在特殊情况下主只是想发送数据到从属，并不需要从从属（即半双工操作），接收数据的SPI从机接收数据时的最大数据传输速率（比特/秒）的1/4系统时钟频率。这是主问题SCK，NSS和串行输入数据同步与从属的系统时钟。

附录B 外文文献

The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multimaster environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode.

The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3 and 4-wire mode.

The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register.

The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave isnot selected (NSS = 1) in 4-wire slave mode.

1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave.

NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus.

3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 o perates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device.

A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift regist er to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT.

When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault w ill generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.

3-wire single-master mode is active when NSSMD1(SPI0CN.3)=0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins.

4-wire single-master mode is active when NSSMD1 (SPI 0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins.

When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are double-buffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer.

When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.

3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and re-enabling SPI0 with the SPIEN bit.

2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes.

3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.

4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost.

Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. Note that CKPHA must be set to‘0’on both the master and slave SPI when communicating between two of the following devices: C8051F04x, C8051F06x, C8051F12x/13x, C8051F31x, C8051F32x, and C8051F33x.

The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.

附录A 译文

附录B 外文文献