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年    月    

摘  要
MCS-51单片机是在一块芯片中集成了CPU、RAM、ROM、定时器/计数器和多功能I/O等一台计算机所需要的基本功能部件，是业界广泛使用的单片机系列。基于FPGA平台的8051单片机CPU核与传统MCS-51单片机完全兼容，但速度约为传统单片机的 20倍，且在FPGA内可轻松的集成许多高性能系统功能，这将使系统的设计效率和系统性能获得极大的提高，这也是现代电子设计技术的发展方向。本课题用硬件描述语言设计MCS-51 CPU核，从CPU的总体结构到局部功能的实现采用了自顶向下的设计方法和模块化的设计思想，利用FPGA，设计实现了八位CPU核。本设计的CPU兼容51指令，在时钟频率和指令的执行效率指标上均优于传统的MCS-51CPU。本设计以硬件描述语言代码形式存在，可与任何综合库、工艺库以及FPGA结合开发出用户需要的固核和硬核，可读性好，易于扩展使用，易于升级，比较有实用价值。本设计通过FPGA验证。

关键字：Verilog HDL；   CPU；   FPGA

ABSTRACT
MCS-51 MCU is a single chip integrated CPU, RAM, ROM, timer / counters and multi-function I / O such as a computer's basic features required, is the industry's widely used microcontroller series. 8051 FPGA-based CPU platform with the traditional core is fully compatible with MCS-51 microcontroller, but the speed is about 20 times that of traditional single chip, and the FPGA can be easily integrated within a number of high-performance system functions, which will enable the design of the system efficiency and system Be greatly improved performance, which is the development of modern electronic design direction. The issue with the hardware description language design MCS-51 CPU core, from the CPU to the local function of the overall structure of the realization of using top-down design and modular design, the use of FPGA, design and implementation of the eight CPU cores. The CPU model in this paper can execute the MCS-51MCU assemble language instruction sets, and is better than the traditional MCS-51 MCU on both clock frequency and the execution efficiency of the instruction. This design was existed in a form of HDL source code，which can be reused in many SoC designs．This model can be read easily, updated easily and extended freely, so it has a practical value in SoC design．This design was implemented on FPGA.

 Keywords:  Verilog HDL ；  CPU ；  FPGA

目  录
摘  要
Abstract
第1章 绪论 ...1
1.1选题背景……………………………………………………………………………………1
1.2国内外发展及现状…………………………………………………………………………1
  1.3课题的主要内容……………………………………………………………………………2
第2章CPU的结构及设计…………………………………………………………..4
2.1 CPU的简介…………………………………………………………………………………4
2.2 CPU的结构…………………………………………………………………………………4
2.2.1 时钟发生器…………………………………………………………………………..

4 2.2.2 指令寄存器…………………………………………………………………………..5
2.2.3 累加器………………………………………………………………………………..6
2.2.4 算术运算器…………………………………………………………………………..6
2.2.5 数据控制器…………………………………………………………………………..7
2.2.6 地址多路器……………………………………………………………………………8
2.2.7程序计数器……………………………………………………………………………8
2.2.8 状态控制器…………………………………………………………………………..9
2.2.9 外围模块…………………………………………………………………………….11
第3章 CPU的功能………………………………………………………………….13
3.1 CPU的操作………………………………………………………………………………….13
    3.1.1 系统的复位和启动操作……………………………………………………………..13
    3.1.2 总线读操作…………………………………………………………………………..13
    3.1.3 总线写操作……………………………………………………………………………13
3.2 CPU的寻址方式和指令集………………………………………………………………… 14
3.3 汇编…………………………………………………………………………………………14
第4章 CPU的仿真和验证…………………………………………………………...16
4.1 CPU模块的仿真…………………………………………………………………………… 16
4.2 CPU模块的综合…………………………………………………………………………… 18
  4.3 CPU模块的优化和优局布线……………………………………………………………… 25
第5章 总结和展望…………………………………………………………………...27
参考文献……………………………………………………………………………..28
致  谢…………………………………………………………………………………29
附  录…………………………………………………………………………………30